Each core has some 32-bit information registers described below. These are offsets into the area 0xF00-0xFFF in the MMIO.
(I've marked those that we don't use yet)
0x08 sbipsflag (*) 0x18 sbtpsflag 0x48 sbtmerrloga (*) 0x50 sbtmerrlog (*) 0x60 sbadmatch3 (*) 0x68 sbadmatch2 (*) 0x70 sbadmatch1 (*) 0x90 sbimstate 0x94 sbintvec 0x98 sbtmstatelow 0x9c sbtmstatehigh 0xa0 sbbwa0 (*) 0xa8 sbimconfiglow 0xac sbimconfighigh (*) 0xb0 sbadmatch0 (*) 0xb8 sbtmconfiglow (*) 0xbc sbtmconfighigh (*) 0xc0 sbbconfig (*) 0xc8 sbbstate (*) 0xd8 sbactcnfg (*) 0xe8 sbflagst (*) 0xf8 SB_ID_LO 0xfc SB_ID_HI
SB_ID_HI
Bits |
31-16 |
15 |
14 - 12 |
11 - 4 |
3 - 0 |
Meaning |
Core Vendor ID |
Core ID |
Core Revision Extension |
Core ID |
Core Revision |
Core Vendor ID Table
Core Vendor ID |
Vendor |
0x4243 |
Broadcom |
Core Revision
To find the Core Revision, read bits 15-0 of SB_ID_HI then mask with 0x7000, then right shift by 8 (This is the Core Revision Extension Field). Bitwise OR the Core Revision Extension Field with the last 4 bits of SB_ID_HI (the Core Revision Field).
Core ID
Finding the Core ID
Read bits 15 - 4 of SB_ID_HI, then mask with 0x8FF0 and shift right by 4
Core ID Table
Core ID |
Type |
0x800 |
ChipCommon Core |
0x801 |
iline20 Core |
0x803 |
SDRAM Core |
0x804 |
|
0x805 |
MIPS Core |
0x806 |
ENET MAC Core |
0x807 |
V90 Codec Core |
0x808 |
USB 1.1 Host/Device |
0x809 |
ADSL Core |
0x80A |
iline100 Core |
0x80B |
IPSEC Core |
0x80D |
PCMCIA Core |
0x80E |
Internal Memory Core |
0x80F |
MEMC SDRAM Core |
0x811 |
External Interface Core |
0x812 |
802.11 MAC Core |
0x816 |
MIPS 3302 Core |
0x817 |
USB 1.1 Host Core |
0x818 |
USB 1.1 Device Core |
0x819 |
USB 2.0 Host Core |
0x81A |
USB 2.0 Device Core |
0x81B |
SDIO Host Core |
0x81C |
Roboswitch Core |
0x81D |
Parallel ATA Core |
0x81E |
Serial ATA & XOR DMA Core |
0x81F |
Gigabit Ethernet Core |
0x820 |
|
0x821 |
MIMO PHY Core |
0x822 |
SRAM Controller Core |
0x823 |
MINI MAC/PHY Core |
0x824 |
ARM 1176 Core |
0x825 |
ARM 7tdmi Core |
SB_ID_LO
Bits |
31-28 |
27-24 |
23-20 |
19-17 |
16 |
Meaning |
SB Revision |
Initiator Ports |
Target Ports |
Cycle Counter Width |
First Initiator |
Bits |
15-12 |
11-8 |
7 |
6 |
5-2 |
1-0 |
Meaning |
Max Backplane Latency |
Min Backplane Latency |
Initiator |
Sync |
# of Adresss Ranges Supported |
Config Space |
sbtmstatelow
Mask |
Usage |
0x00000001 |
Reset |
0x00000006 |
Reject |
0x00010000 |
Clock Enable |
0x00020000 |
Force Gated Clocks On |
0x3FFC0000 |
Core Specific Flags (coreflagslow) |
0x40000000 |
PME Enable |
0x80000000 |
BIST Enable |
sbtmstatehigh
Mask |
Usage |
0x00000001 |
S Error |
0x00000002 |
Interrupt |
0x00000004 |
Busy |
0x00000020 |
Timeout |
0x1FFF0000 |
Core Specific Flags (coreflagshigh) |
0x10000000 |
Core Supports 64 bit DMA |
0x20000000 |
Gated Clock Request |
0x40000000 |
BIST Failed |
0x80000000 |
BIST Complete |
sbimstate
Mask |
Usage |
0x0000000F |
Pipe Count |
0x00000030 |
Arbitration Policy |
0x00020000 |
Inband Error |
0x00040000 |
Timeout |
0x01800000 |
Busy |
0x02000000 |
Reject |
sbtpsflag
Mask |
Usage |
0x0000003F |
Backplane Flag # |
0x00000040 |
Interrupt is always sent on the Backplane |
sbintvec
Backplane Interrupt Vector Register - marks the interrupts with a mask
sbimconfiglow
Mask |
Usage |
0x00000007 |
Service Timeout |
0x00000070 |
Request Timeout |
0x00FF0000 |
Connection ID |